A computer system relies upon a high-speed memory bus to transfer data between system memory and a central processing unit (CPU). A separate lower speed input/output (I/O) bus is typically used for I/O operations between a CPU and a slave device, such as a print driver. Prior art computer systems have used lower speed I/O buses for data transfer between system memory and a CPU. This technique considerably increases the time required for reading and writing data to memory. Thus, prior art computer systems have provided a high-speed memory bus for the system memory and a separate low-speed I/O bus for slave devices. It would be highly desirable to eliminate this redundancy in hardware and utilize a single high-speed memory bus for data transfers between system memory and a CPU, and for controlling operations between a CPU and a slave device. Such a system should not require a reconfiguration of system memory. In other words, the slave device should operate in conjunction with the existing system memory access architecture.
Prior art techniques for transferring data between a CPU and a slave device on a low speed I/O bus is a two step process. First, the CPU, also called a master device, generates a write request, a memory mapped I/O address, and data onto the I/O bus. A slave device, such as a print driver, reads the information, and then sends an acknowledgement back to the master device. The time between the write request and the data acknowledgement is the data transfer acknowledgement latency.
The data bandwidth of prior art computer buses is limited by this data transfer acknowledgement latency. The data transfer acknowledgement latency problem is more fully appreciated with reference to FIG. 1. A write request is sent from a master device. An acknowledgement signal signifying the receipt of the data is then sent from a slave device several cycles later. Only after this acknowledgement signal is received can the master device issue another write request, as shown in FIG. 1. On a synchronous bus, this data transfer acknowledgement latency doubles or triples the number of clock cycles required to send a single write request.
To mitigate the bandwidth expense associated with data transfer acknowledgement latencies, burst mode data transfers were developed. In a burst mode data transfer, only one acknowledgement is required for a large block of data. Thus, burst mode data transfer amortizes the data transfer acknowledgement latency over larger blocks of write data.
Unfortunately, the burst mode data transfer technique has associated problems. First, the data transfer acknowledgement latency is just as long as in the traditional data transfer case shown in FIG. 1. Another problem is that the burst mode data transfer requires that the same amount of data always be transferred. Frequently, the amount of data to be sent is less than the required amount for burst mode data transfer. This problem may be alleviated by special techniques for masking the unused portion of the burst mode data. However, this results in added system complexity and expense.
Another problem with burst mode data transfers is that they require a fixed byte order. It is frequently desirable to transfer data without conforming to a fixed byte order, for instance in an overlapping copy operation.
Burst mode data transfer techniques have a restricted address range. That is, only addresses within the burst size can be accessed in the burst mode. It is desirable to access any address in any order. This capability is especially important in graphics applications. For example, when drawing vectors and triangles, where addresses are localized, but they are in random directions.
Thus, it would be highly desirable to provide a computer system data bus that reduces data transfer acknowledgement latency overhead. Such a system should avoid the problems attendant with burst mode data transfers.